1. Field of the Invention
The present invention relates to a circuit arrangement for identifying specific bit patterns, particularly bit patterns forming synchronization signals and check loop signals, in binary signals appearing serially on a plurality of signal lines, comprising a register arrangement for serial receiving of the binary signals and a comparator arrangement which respectively compares the prescribed plurality of bits of the received binary signals to at least one predetermined bit combination and which, given identification of a coincidence between the respective bit combination and the bits of the received binary signals acquired in the prescribed plurality, transmits a status signal indicating a specific bit pattern.
2. Description of the Prior Art
A circuit arrangement is already known (German Pat. No. 31 03 574, fully incorporated herein by this reference) with whose assistance the synchronism between the envelope clock pulses derived from locally generated bit clock pulses and the synchronization bits of a prescribed polarity sequence regularly contained at a prescribed bit location in envelopes of a binary coded signal is produced and maintained. For this purpose, the appertaining known circuit arrangement comprises a shift register to which the individual, serially appearing binary signals are supplied. A circuit arrangement which respectively actively connects only the output of one shift register stage to the input of a comparator arrangement is connected to the outputs of the individual shift register stages. This comparator arrangement compares the respective bits supplied thereto via a switch arrangement to a bit of a prescribed bit sequence. Given lack of coincidence of the bits compared to one another in the comparator arrangement in such a manner, the comparator arrangement emits a setting signal to the switch arrangement whose setting is modified in response thereto. Only given identification of a coincidence of the bits compared to one another does the comparator arrangement emit a status signal which, on the one hand, indicates the identification of a specific bit pattern and which, on the other hand, leads to the disablement of the switch arrangement. Although it is possible with the assistance of this known circuit arrangement to identify specific bit patterns in a serially appearing binary signal, it is not possible without further measures to identify such bit patterns which are composed of immediately successive bits. Further, it is not possible without further measures, given the known circuit arrangement, to check binary signals appearing serially on a plurality of signal lines with respect to the existence of specific bit patterns.